System-on-Chip (SoC) Physical Design Engineer

System-on-Chip (SoC) Physical Design Engineer

Location United States

Employment Type: Full-time

Education: B.S. in Electrical Engineering Experience: 5+ years

Position Summary

We are seeking an experienced System-on-Chip (SoC) Physical Design Engineer to drive advanced-node designs from floorplanning through place and route, timing closure, physical verification, power integrity, signoff, and tapeout. The ideal candidate is highly hands-on, technically strong, and able to independently diagnose complex implementation issues while collaborating closely with front-end, verification, DFT, package, CAD, and foundry teams.

Key Responsibilities

• Own the complete SoC physical design flow from netlist and UPF handoff through floorplanning, placement, CTS, routing, ECO, timing closure, physical verification, signoff, and tapeout.
• Perform chip/block floorplanning, macro placement, I/O and pin planning, power-domain planning, power-grid design, congestion analysis, and routing-resource planning.
• Drive place and route, physical optimization, CTS, routing, and ECO implementation using Cadence Innovus.
• Drive timing closure across multiple modes and PVT corners using PrimeTime or Tempus with MMMC methodologies.
• Set up, run, debug, and close Calibre LVS, DRC, antenna, wirebond, and WLCSP checks; interpret foundry rules and implement manual or automated fixes in Innovus.
• Perform RC extraction with Quantus and IR-drop/electromigration analysis with Voltus.
• Perform RTL- and gate-level power analysis using Cadence Joules.
• Collaborate with RTL and verification engineers using Xcelium or VCS waveforms to debug logic, timing, and integration issues.
• Use AI responsibly to find innovative solutions that save cycle time and reduce human errors.
• Participate in tapeout readiness reviews and ensure completion of timing, physical verification, power integrity, low-power, and foundry signoff requirements.

Required Qualifications

• B.S. degree in Electrical Engineering.
• Minimum 5 years of hands-on SoC or ASIC physical design experience, including floorplanning, place and route, ECO, timing closure, physical verification, and tapeout.
• Advanced-node tapeout experience, preferably including 22 nm, 12 nm, and 7 nm technologies.
• Extensive hands-on experience with Cadence Innovus.
• Hands-on experience with UPF low-power design flow from synthesis through place and route; able to develop and debug UPF based on architectural, RTL power-domain specifications, and power intent.
• Able to set up and run logic synthesis using Synopsys Design Compiler or Cadence Genus.
• Extensive static timing analysis and timing closure experience using Synopsys PrimeTime or Cadence Tempus.
• Extensive CTS experience in Innovus, including clock-tree tuning and balancing for skew, latency, power, and robustness across PVT corners.
• Logic equivalence check (LEC) using Conformal.
• Good familiarity with DFT concepts and related physical design methodologies such as scan chain reordering, power analysis/timing analysis modes, etc.
• Hands-on experience setting up and running Siemens Calibre LVS, DRC, antenna, wirebond, and WLCSP checks.
• Ability to read and interpret foundry design rule manuals and resolve DRC issues manually or through automated Innovus flows.
• Experience using Cadence Quantus for RC extraction.
• Experience using Cadence Voltus for static/dynamic IR-drop and electromigration analysis.
• Experience using Cadence Joules for RTL- and gate-level power analysis.
• Familiarity with RTL and gate-level simulation using Cadence Xcelium or Synopsys VCS and ability to analyze waveforms with front-end engineers.
• Strong understanding of SDC, generated clocks, clock groups, false paths, multicycle paths, derates, OCV/AOCV/POCV, setup/

Technical Expertise

• Experience with 22nm, 12nm, 7nm design rules, physical design flows, standard cells, memories, PVT corners and their characteristics, and pitfalls.
• Low-power implementation: deep knowledge of, and implementation experience of, power domains, isolation, level shifters, retention, power switches, always-on logic, and power-state tables.
• Logic equivalence checking: able to set up tool scripts and debug/resolve non-equivalence for RTL vs. RTL, RTL vs. gate, and gate vs. gate, with UPF.
• Physical design optimization: congestion, utilization, routability, area, leakage, dynamic power, and manufacturability.
• Signal integrity: crosstalk, coupling capacitance, noise, shielding, spacing, layer assignment, and delta-delay effects.
• Power-grid design and optimization, including straps, vias, decap insertion, current density, and EM/IR mitigation.
• Advanced-node signoff methodologies, including multi-corner/multi-mode analysis and foundry tapeout requirements.
• Mixed-signal integration experience, including signal noise isolation, analog-digital power isolation, impedance matching, differential signal routing, etc.

Preferred Qualifications

• Multiple successful SoC or ASIC tapeouts at 12nm node, including ownership of full chip-level implementation.
• Experience with hierarchical and flat physical design methodologies.
• Experience with complex multi-voltage, multi-power-domain SoCs.
• Physical design experience with high-speed interfaces such as PCIe, or other complex IP.
• Familiarity with DFT, scan, CDC/reset considerations, package constraints, bump planning, wirebond, WLCSP, or flip-chip implementation.
• RTL expertise.
• Agentic design experience is a plus.

Automation and Scripting

• Proficiency with Tcl and at least one additional scripting language such as Python, Perl, or shell scripting.
• Ability to automate physical design, signoff, reporting, regression, and data-analysis tasks.
• Experience developing or maintaining implementation flows and reusable scripts is highly desirable.

Personal Attributes

• Highly hands-on, detail-oriented, and technically rigorous.
• Able to independently troubleshoot difficult design and signoff problems with minimal supervision.
• Strong ownership mindset with the ability to drive assigned blocks or chip-level responsibilities through closure.
• Clear communicator who works effectively across front-end, verification, DFT, package, CAD, and foundry teams.
• Comfortable working in a fast-paced semiconductor development environment and prioritizing multiple closure issues under schedule pressure.
• Willing to share knowledge, help teammates, and contribute to continuous improvement of design methodology and flows.

Location

• USA. Position could be located anywhere in the U.S.A. (remote), or in-person in the Bay Area

What We Offer

• Work on production-oriented edge-AI technology from model import through silicon execution.
• A collaborative environment with significant technical ownership and impact.
• A competitive compensation package including stock options

Apply Now