Startups

anysilicon.com

Next-Gen System Cache ASIC Digital Design Engineer

<meta name="twitter:description" content="{"overview":"Qualcomm Technologies, Inc. is seeking an ASIC Engineer to join its Engineering Group, focusing on the design and development of" /> You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 14 Views Next-Gen System Cache ASIC Digital Design Engineer

Join Job Mailing List

Published Date: October 08, 2026

Apply

Qualcomm, San Diego, CA

Job Description

Qualcomm Technologies, Inc. is seeking an ASIC Engineer to join its Engineering Group, focusing on the design and development of high-performance, low-power System-On-A-Chip (SoC) products. The role involves collaboration with cross-functional teams to drive innovation and optimize hardware design for next-generation technologies.

Responsibilities

  • Micro-architect, design, and validate RTL for SoC Interconnects, Cache, and memory subsystems.
  • Identify advanced optimization techniques for hardware design to enhance performance, power efficiency, and cost.
  • Evaluate hardware feasibility for complex algorithms and requirements.
  • Develop microarchitecture specifications for new generation designs.
  • Create RTL corresponding to the developed microarchitecture.
  • Conduct verification and debugging activities throughout project cycles.
  • Optimize silicon cost and improve clock speed.
  • Troubleshoot silicon issues related to the design. Qualifications:
  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5; OR
  • Master's degree in the same fields with a GPA > 3.5; OR
  • PhD in a relevant field.
  • 2 years of ASIC design experience with a Bachelor's; 1 year with a Master's; or relevant experience for PhD holders. Skills:
  • Experience in Verilog/SystemVerilog design and Synopsys synthesis.
  • Knowledge of low power design and test plan development.
  • Familiarity with Computer Architecture and Computer Arithmetic.
  • Proficiency in C/C++/Python programming languages.
  • Experience in designing RTL for CPU and cache controller blocks is a plus.
  • Strong communication skills and a collaborative team spirit.

Recent Stories

MPW Run: Cost, Schedule & Booking Tool

Read More »

TSMC MPW: CyberShuttle, Cost, Schedule & Access

Read More »

High-end packaging: a market set to nearly quintuple by 2031

Read More »

IC Prototype Packaging: Options, Cost & Suppliers

Read More »

Silicon Interposer vs Organic Interposer vs Glass Interposer: Which Is Best?

Read More »

2.5D vs 3D Packaging: What Is the Difference?

Read More »

VQFN Package: What It Is, Sizes, Price & PCB Design

Read More »

QFN vs QFP: What Is the Difference and Which Package Should You Choose?

Read More »

Get Price for ASIC Design Services

Get Price for IC Packaging

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

  • ASIC Design Services
  • Verification
  • Packaging & Wafer
  • Semiconductor IP

Work Email

Get Free Recommendations

Free • No obligation • Response within 24 hours Get Price Offers From ASIC Design Houses Wafer Foundries Chip Packaging

IC Testing

IP Core Vendors

FPGA Design

Featured Vendor

SigmanticAI

Welcome New Vendors

  • TOPPAN Technical Design Center
  • Digicomm Semiconductor
  • Tekmos
  • BitSim Now
  • AnaBatIC Semiconductor

Recent Posts

  • GlobalFoundries Wins $2 Billion TSMC CoWoS Interposer Deal, Expanding U.S. Advanced Packaging Supply
  • ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
  • Xiphera launches nQrux® Root of Trust with Post-Quantum Cryptography
  • MPW Run: Cost, Schedule & Booking Tool
  • TSMC MPW: CyberShuttle, Cost, Schedule & Access
  • High-end packaging: a market set to nearly quintuple by 2031

Most Popular Blog Posts

  • Semiconductor Manufacturing Cost Breakdown | Wafer, Packaging, Test & ASIC Cost Factors
  • TSMC and Sony Plan Image Sensor Joint Venture in Japan
  • Semiconductor Design and Verification Services | ASIC, SoC & IC Development Partners
  • ASIC Design Services for Startups | From Idea to Silicon
  • Custom ASIC Solutions | Find ASIC Design & Turnkey Chip Development Partners

Tools

  • ASIC Price Calculator
  • IC Packages Price Calculator
  • Die Per Wafer Calculator
  • Bonding Diagram Tool
  • CPU IP Core Search Engine
  • Find Consultants

We are using cookies to give you the best experience on our website. You can find out more about which cookies we are using or switch them off in settings. Accept

Reject

Close GDPR Cookie Settings

Privacy Overview

Strictly Necessary Cookies 3rd Party Cookies

Privacy Overview

This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.

Strictly Necessary Cookies

Strictly Necessary Cookie should be enabled at all times so that we can save your preferences for cookie settings. Enable or Disable Cookies

Enabled

Disabled

3rd Party Cookies This website uses Google Analytics to collect anonymous information such as the number of visitors to the site, and the most popular pages. Keeping this cookie enabled helps us to improve our website. Enable or Disable Cookies

Enabled

Disabled

Enable All Reject All

Sourced 2026-10-09