ASIC DFT Engineer

ASIC DFT Engineer - AnySilicon

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Published Date: October 15, 2026

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Cisco Systems, San Jose, CA

Job Description

Join Cisco's Silicon One team as an ASIC Engineer focused on Design-for-Test (DFT) in the development of innovative hardware platforms for the AI era. This role involves collaboration with front-end RTL and backend physical design teams to drive DFT requirements and contribute to next-generation networking chips. You will play a key role in the implementation flow and post-silicon validation phases, ensuring high-quality chip designs.

Responsibilities

Collaborate with front-end RTL and backend physical design teams to understand chip architecture.
Drive DFT requirements early in the design cycle.
Lead the DFT and quality process throughout the implementation flow.
Participate in post-silicon validation and debug activities.
Work with ATE patterns and P1687 standards. Qualifications:
Bachelor's or Master's Degree in Electrical or Computer Engineering.
Minimum of 3 years of experience in DFT, test, and silicon engineering. Skills:
Experience with JTAG protocols, Scan and BIST architectures.
Familiarity with ATPG and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime.
Proficient in gate-level simulation and debugging with VCS and other simulators.
Post-silicon validation experience with DFT patterns.
Verilog design experience and functional verification skills.

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ASIC DFT Engineer