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Published Date: October 05, 2026
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Meta, 1180 Discovery Way, Sunnyvale, CA 94089
Job Description
Meta is seeking an experienced ASIC Design Verification Engineer specializing in Design for Testability (DFT) to join its Infrastructure Silicon organization. This role focuses on developing and verifying DFT architectures for custom ASICs and SoC designs that support Meta's data center infrastructure. The engineer will ensure silicon manufacturability, testability, and quality, collaborating with various teams to validate DFT structures using advanced methodologies.
Responsibilities
- Define and implement DFT verification plans for scan insertion, ATPG, BIST, JTAG, and boundary scan structures.
- Develop and maintain UVM-based and C/C++ testbenches for DFT logic verification.
- Drive verification closure using metrics like functional coverage and DFT-specific structural coverage goals.
- Collaborate with DFT architects and design engineers to validate DFT insertion methodologies.
- Debug and root-cause functional and structural failures in DFT logic.
- Develop and validate ATPG test pattern generation flows to meet quality and fault coverage targets.
- Apply formal verification techniques to ensure correctness of DFT control logic and test mode isolation.
- Partner with emulation and post-silicon validation teams for DFT bring-up and correlation of verification results with silicon outcomes.
- Build and maintain verification infrastructure and automation flows to enhance DFT verification efficiency.
- Contribute to the continuous improvement of DFT verification methodologies and tools. Qualifications:
- 6 years of hands-on experience in ASIC design verification using SystemVerilog and UVM-based methodologies.
- 6 years of experience with DFT verification, including scan insertion and ATPG pattern validation.
- Proficiency with EDA tools for DFT insertion and simulation, along with scripting skills in Python, Tcl, Perl, or Shell.
- Experience in driving IP, sub-system, or SoC-level verification closure. Skills:
- Expertise in DFT verification techniques including scan insertion, ATPG, BIST, and JTAG.
- Proficient in developing UVM-based testbenches and automation scripts.
- Strong debugging skills for DFT logic and collaboration with design teams.
- Knowledge of formal verification techniques and high-speed interface DFT structures.
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