Startups

anysilicon.com

SoC Power Design Engineer [Engineer – Staff Eng]

<meta name="twitter:description" content="{"overview":"Qualcomm, a leader in technology innovation, is seeking talented ASIC Design Engineers to join its SoC and ASIC Design organization. This role" /> You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 7 Views SoC Power Design Engineer [Engineer – Staff Eng]

Join Job Mailing List

Published Date: September 26, 2026

Apply

Qualcomm, San Diego, CA

Job Description

Qualcomm, a leader in technology innovation, is seeking talented ASIC Design Engineers to join its SoC and ASIC Design organization. This role offers the opportunity to work on cutting-edge projects in high-performance computing, AI, mobile, automotive, and next-generation semiconductor technologies, contributing to the development of smarter, more connected solutions.

Responsibilities

  • Participate in the architecture, design, implementation, integration, and optimization of ASIC, SoC, and IP solutions.
  • Develop and validate design solutions that meet performance, power, area, timing, and quality objectives.
  • Contribute to ASIC development activities including RTL design, static timing analysis, timing closure, synthesis, verification, and silicon bring-up.
  • Collaborate with cross-functional teams to deliver complex SoC solutions.
  • Analyze and resolve design, implementation, and verification challenges using sound ASIC engineering practices.
  • Participate in design reviews and contribute technical expertise to drive project execution and quality.
  • Develop and enhance design flows, methodologies, automation frameworks, and engineering tools to improve productivity and quality.
  • Support continuous improvement efforts by applying silicon learnings and feedback to future designs, processes, and methodologies.
  • Effectively communicate technical concepts and collaborate across teams. Qualifications:
  • Bachelor's degree in Science, Engineering, or related field with 4 years of relevant experience, or a Master's degree with 3 years, or a PhD with 2 years of experience in ASIC design, verification, validation, or integration. Skills:
  • Experience in ASIC, FPGA, or SoC design and development.
  • Understanding of digital design fundamentals, computer architecture, and semiconductor development processes.
  • Experience with industry-standard ASIC design, implementation, verification, and/or timing analysis tools.
  • Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.
  • Strong analytical, problem-solving, communication, and teamwork skills.

Recent Stories

Hire ASIC Verification Engineers

Read More »

Hire Physical Design Engineers | RTL-to-GDSII & P&R Contractors

Read More »

Hire ASIC Design Engineers

Read More »

Hire Analog Layout Designers

Read More »

Hire Analog & Mixed-Signal IC Designers

Read More »

CEO Talk: Kazushige Koshika, President of TOPPAN Technical Design Center Inc.

Read More »

Digital Isolator & Isolated Interface IC Alternatives

Read More »

High-Voltage DC/DC Converter ICs: 40V, 60V, 80V & 100V Alternatives

Read More »

Get Price for ASIC Design Services

Get Price for IC Packaging

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

  • ASIC Design Services
  • Verification
  • Packaging & Wafer
  • Semiconductor IP

Work Email

Get Free Recommendations

Free • No obligation • Response within 24 hours Get Price Offers From ASIC Design Houses Wafer Foundries Chip Packaging

IC Testing

IP Core Vendors

FPGA Design

Featured Vendor

Silicon Creations

Welcome New Vendors

  • TOPPAN Technical Design Center
  • Digicomm Semiconductor
  • Tekmos
  • BitSim Now
  • AnaBatIC Semiconductor

Recent Posts

  • Sofics Extends Interface Voltage Options in TSMC FinFET and Nanosheet Technologies
  • Synopsys and TSMC Partner to Accelerate AI Systems Innovation with Agentic AI and Advanced Design
  • TES Electronic Solutions Introduces an Over-Voltage Lockout IP for the Protection of Battery-Powered Systems in X-FAB’s XT018 – 0.18µm BCD-on-SOI Technology.
  • Hire ASIC Verification Engineers
  • Hire Physical Design Engineers | RTL-to-GDSII & P&R Contractors
  • Hire ASIC Design Engineers

Most Popular Blog Posts

  • Semiconductor Manufacturing Cost Breakdown | Wafer, Packaging, Test & ASIC Cost Factors
  • TSMC and Sony Plan Image Sensor Joint Venture in Japan
  • Semiconductor Design and Verification Services | ASIC, SoC & IC Development Partners
  • TO-247 Package: Complete Guide for TO-247
  • ASIC Design Services for Startups | From Idea to Silicon

Tools

  • ASIC Price Calculator
  • IC Packages Price Calculator
  • Die Per Wafer Calculator
  • Bonding Diagram Tool
  • CPU IP Core Search Engine
  • Find Consultants

We are using cookies to give you the best experience on our website. You can find out more about which cookies we are using or switch them off in settings. Accept

Reject

Close GDPR Cookie Settings

Privacy Overview

Strictly Necessary Cookies 3rd Party Cookies

Privacy Overview

This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.

Strictly Necessary Cookies

Strictly Necessary Cookie should be enabled at all times so that we can save your preferences for cookie settings. Enable or Disable Cookies

Enabled

Disabled

3rd Party Cookies This website uses Google Analytics to collect anonymous information such as the number of visitors to the site, and the most popular pages. Keeping this cookie enabled helps us to improve our website. Enable or Disable Cookies

Enabled

Disabled

Enable All Reject All

Bron 2026-09-26