Startups

anysilicon.com

Senior IC Layout design Engineer

Senior IC Layout design Engineer - AnySilicon You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 10 Views Senior IC Layout design Engineer

Join Job Mailing List

Published Date: October 11, 2026

Apply

Advanced Micro Devices, Inc, 2100 Logic Drive, San Jose, CA 95124

Job Description

At AMD, we harness technology to tackle the world's most pressing challenges, from healthcare advancements to AI innovations. Join us in shaping the future through cutting-edge processor design and product development, and advance your career while contributing to technology that propels the world forward.

Responsibilities

  • Design high-speed, high-performance SerDes analog mixed-signal circuits according to project specifications.
  • Implement block-level physical designs, including floor-planning, power distribution, and signal routing.
  • Engage in post-layout circuit performance analysis and integration activities at block/IP/chip levels.
  • Estimate project schedules, track progress, and report status clearly.
  • Contribute to defining layout methodologies and workflows.
  • Drive initiatives for layout productivity improvements, including pcell development and automation.
  • Supervise layout resources, assess layout quality, and provide feedback to design teams. Qualifications:
  • Bachelor's degree in Electrical Engineering/Computer Engineering or equivalent IC layout training with relevant experience. Skills:
  • Experience in layout design for lower process nodes (7nm or below).
  • Strong understanding of analog and mixed-signal layout fundamentals, including IR, EM, capacitances, and RC delay.
  • Proficient in high-speed signal routing and shielding techniques.
  • Skilled in physical design verifications (LVS/DRC/ERC/ANT/ESD).
  • Familiarity with circuit design concepts and IC manufacturing processes.
  • Experience with high-speed SerDes blocks and PLLs in advanced Fin-FET processes is advantageous.
  • Knowledge of digital integration flows and Cadence SKILL programming, as well as other languages like Perl, Python, or Tcl.
  • Excellent communication skills and ability to collaborate with remote teams across different time zones.

Recent Stories

MPW Run: Cost, Schedule & Booking Tool

Read More »

TSMC MPW: CyberShuttle, Cost, Schedule & Access

Read More »

High-end packaging: a market set to nearly quintuple by 2031

Read More »

IC Prototype Packaging: Options, Cost & Suppliers

Read More »

Silicon Interposer vs Organic Interposer vs Glass Interposer: Which Is Best?

Read More »

2.5D vs 3D Packaging: What Is the Difference?

Read More »

VQFN Package: What It Is, Sizes, Price & PCB Design

Read More »

QFN vs QFP: What Is the Difference and Which Package Should You Choose?

Read More »

Get Price for ASIC Design Services

Get Price for IC Packaging

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

  • ASIC Design Services
  • Verification
  • Packaging & Wafer
  • Semiconductor IP

Work Email

Get Free Recommendations

Free • No obligation • Response within 24 hours Get Price Offers From ASIC Design Houses Wafer Foundries Chip Packaging

IC Testing

IP Core Vendors

FPGA Design

Featured Vendor

SYNERGIE CAD PSC

Welcome New Vendors

  • TOPPAN Technical Design Center
  • Digicomm Semiconductor
  • Tekmos
  • BitSim Now
  • AnaBatIC Semiconductor

Recent Posts

  • GlobalFoundries Wins $2 Billion TSMC CoWoS Interposer Deal, Expanding U.S. Advanced Packaging Supply
  • ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
  • Xiphera launches nQrux® Root of Trust with Post-Quantum Cryptography
  • MPW Run: Cost, Schedule & Booking Tool
  • TSMC MPW: CyberShuttle, Cost, Schedule & Access
  • High-end packaging: a market set to nearly quintuple by 2031

Most Popular Blog Posts

  • Semiconductor Manufacturing Cost Breakdown | Wafer, Packaging, Test & ASIC Cost Factors
  • TSMC and Sony Plan Image Sensor Joint Venture in Japan
  • Semiconductor Design and Verification Services | ASIC, SoC & IC Development Partners
  • ASIC Design Services for Startups | From Idea to Silicon
  • Custom ASIC Solutions | Find ASIC Design & Turnkey Chip Development Partners

Tools

  • ASIC Price Calculator
  • IC Packages Price Calculator
  • Die Per Wafer Calculator
  • Bonding Diagram Tool
  • CPU IP Core Search Engine
  • Find Consultants

We are using cookies to give you the best experience on our website. You can find out more about which cookies we are using or switch them off in settings. Accept

Reject

Close GDPR Cookie Settings

Privacy Overview

Strictly Necessary Cookies 3rd Party Cookies

Privacy Overview

This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.

Strictly Necessary Cookies

Strictly Necessary Cookie should be enabled at all times so that we can save your preferences for cookie settings. Enable or Disable Cookies

Enabled

Disabled

3rd Party Cookies This website uses Google Analytics to collect anonymous information such as the number of visitors to the site, and the most popular pages. Keeping this cookie enabled helps us to improve our website. Enable or Disable Cookies

Enabled

Disabled

Enable All Reject All

Bron 2026-10-11