<meta name="twitter:description" content="{"overview":"Tensordyne, a leading AI system solution company, specializes in high-performance, low-power generative AI inference systems. With a mission to" /> You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 24 Views Senior ASIC Physical Design Engineer
Join Job Mailing List
Published Date: October 08, 2026
Apply
Tensordyne, Sunnyvale, CA
Job Description
Tensordyne, a leading AI system solution company, specializes in high-performance, low-power generative AI inference systems. With a mission to accelerate multimodal generative AI inference at scale, Tensordyne is at the forefront of innovation in AI technology. The company, headquartered in Sunnyvale, CA, and Munich, Germany, offers a supportive work environment with comprehensive benefits and competitive compensation, aiming to build a healthy and motivated team to drive technological advancements.
Responsibilities
- Lead ASIC front-end physical design and engineering workflow development for generative AI inference products.
- Guide and assist colleagues in improving frontend physical design at both block and full-chip levels.
- Drive optimization, implementation, and exploration of new frontend physical design workflows, including synthesis, formal checks, and power analysis.
- Provide guidance for static timing analysis (STA) and contribute to the full ASIC chip design process.
- Innovate and improve scalable, reliable, high-performance systems and tools for next-generation products.
- Collaborate closely with ASIC team members to understand and enhance their workflows and EDA needs. Qualifications:
- 10 years of hands-on ASIC engineering experience with deep knowledge of VLSI/SoC chip physical design workflows.
- Experience with EDA tools like Cadence/Synopsys (Genus/DC), power analysis, and clock methodology.
- Strong physical design knowledge for front-end optimization using standard EDA tools.
- Experience leading backend design teams with understanding of clock trees, routing, DRC, LVS, and metal fill until artwork release.
- Understanding of STA analysis and constraints for block level and full chip timing analysis.
- Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field. Skills:
- Excellent analytical, written, and verbal interpersonal skills.
- Ability to collaborate productively within a global engineering team in a fast-paced startup environment.
- Strong problem-solving skills with a focus on designing, debugging, and optimizing EDA solutions.
Recent Stories
MPW Run: Cost, Schedule & Booking Tool
Read More »
TSMC MPW: CyberShuttle, Cost, Schedule & Access
Read More »
High-end packaging: a market set to nearly quintuple by 2031
Read More »
IC Prototype Packaging: Options, Cost & Suppliers
Read More »
Silicon Interposer vs Organic Interposer vs Glass Interposer: Which Is Best?
Read More »
2.5D vs 3D Packaging: What Is the Difference?
Read More »
VQFN Package: What It Is, Sizes, Price & PCB Design
Read More »
QFN vs QFP: What Is the Difference and Which Package Should You Choose?
Read More »
Get Price for ASIC Design Services
Get Price for IC Packaging
Find the Right Semiconductor Partner
Tell us what you're building and we'll recommend qualified vendors for your project.
- ASIC Design Services
- Verification
- Packaging & Wafer
- Semiconductor IP
Work Email
Get Free Recommendations
Free • No obligation • Response within 24 hours Get Price Offers From ASIC Design Houses Wafer Foundries Chip Packaging
IC Testing
IP Core Vendors
FPGA Design
Featured Vendor
NTLab
Welcome New Vendors
- TOPPAN Technical Design Center
- Digicomm Semiconductor
- Tekmos
- BitSim Now
- AnaBatIC Semiconductor
Recent Posts
- GlobalFoundries Wins $2 Billion TSMC CoWoS Interposer Deal, Expanding U.S. Advanced Packaging Supply
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- Xiphera launches nQrux® Root of Trust with Post-Quantum Cryptography
- MPW Run: Cost, Schedule & Booking Tool
- TSMC MPW: CyberShuttle, Cost, Schedule & Access
- High-end packaging: a market set to nearly quintuple by 2031
Most Popular Blog Posts
- Semiconductor Manufacturing Cost Breakdown | Wafer, Packaging, Test & ASIC Cost Factors
- TSMC and Sony Plan Image Sensor Joint Venture in Japan
- Semiconductor Design and Verification Services | ASIC, SoC & IC Development Partners
- ASIC Design Services for Startups | From Idea to Silicon
- Custom ASIC Solutions | Find ASIC Design & Turnkey Chip Development Partners
Tools
- ASIC Price Calculator
- IC Packages Price Calculator
- Die Per Wafer Calculator
- Bonding Diagram Tool
- CPU IP Core Search Engine
- Find Consultants
We are using cookies to give you the best experience on our website. You can find out more about which cookies we are using or switch them off in settings. Accept
Reject
Close GDPR Cookie Settings
Privacy Overview
Strictly Necessary Cookies 3rd Party Cookies
Privacy Overview
This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.
Strictly Necessary Cookies
Strictly Necessary Cookie should be enabled at all times so that we can save your preferences for cookie settings. Enable or Disable Cookies
Enabled
Disabled
3rd Party Cookies This website uses Google Analytics to collect anonymous information such as the number of visitors to the site, and the most popular pages. Keeping this cookie enabled helps us to improve our website. Enable or Disable Cookies
Enabled
Disabled
Enable All Reject All