Startups

anysilicon.com

PMIC Reference HW Design Engineer

PMIC Reference HW Design Engineer - AnySilicon <meta name="twitter:description" content="{"overview":"The QCT PMIC Systems group at Qualcomm is seeking a PMIC Reference HW Design Engineer to lead the design and optimization of PMIC PCB for" /> You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 21 Views PMIC Reference HW Design Engineer

Join Job Mailing List

Published Date: October 03, 2026

Apply

Qualcomm, San Diego, CA

Job Description

The QCT PMIC Systems group at Qualcomm is seeking a PMIC Reference HW Design Engineer to lead the design and optimization of PMIC PCB for Qualcomm chipset-based phone designs. This role focuses on creating design guidelines, schematics, layouts, and thermal solutions for test platforms and customer reference designs.

Responsibilities

  • Design customer reference boards and evaluation kits, collaborating with PMIC IC designers and Test HW platform teams to optimize performance and cost.
  • Develop and publish PMIC PCB design guidelines, schematics, BOM selection, and PCB layouts in coordination with CAD engineers.
  • Conduct board-level simulations using Power Integrity and Signal Integrity tools to review and approve hardware designs from various test teams.
  • Characterize and publish performance and cost-optimized reference BOM lists based on component characterization and optimization tests. Qualifications:
  • Bachelor's degree in Electrical Engineering or related field with 5 years of relevant experience, or a Master's degree with 4 years, or a PhD with 2 years of experience.
  • 2 years of experience with IC design tools, PCB design tools, SPICE, MATLAB, Verilog/VHDL, C, or Python. Skills:
  • Experience with common lab test equipment (oscilloscope, spectrum analyzer, logic analyzer, etc.).
  • Knowledge of Power Management PCB design and component selection, including CAD interface.
  • Familiarity with high layer count multilayer boards (6/8/10 layers).
  • Understanding of Signal and Power Integrity issues and ability to use simulators like powerSI, SIWave, or Ansys.

Recent Stories

IC Prototype Packaging: Options, Cost & Suppliers

Read More »

Silicon Interposer vs Organic Interposer vs Glass Interposer: Which Is Best?

Read More »

2.5D vs 3D Packaging: What Is the Difference?

Read More »

VQFN Package: What It Is, Sizes, Price & PCB Design

Read More »

QFN vs QFP: What Is the Difference and Which Package Should You Choose?

Read More »

BGA Packaging Services – Find BGA Assembly Companies

Read More »

QFN Packaging Services – Find a QFN Assembly Company

Read More »

Hire ASIC Verification Engineers

Read More »

Get Price for ASIC Design Services

Get Price for IC Packaging

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

  • ASIC Design Services
  • Verification
  • Packaging & Wafer
  • Semiconductor IP

Work Email

Get Free Recommendations

Free • No obligation • Response within 24 hours Get Price Offers From ASIC Design Houses Wafer Foundries Chip Packaging

IC Testing

IP Core Vendors

FPGA Design

Featured Vendor

Productivity Engineering

Welcome New Vendors

  • TOPPAN Technical Design Center
  • Digicomm Semiconductor
  • Tekmos
  • BitSim Now
  • AnaBatIC Semiconductor

Recent Posts

  • OpenAI and Synopsys Announce GPT-Synopsys: Frontier Intelligence to Revolutionize Chip Design
  • GlobalFoundries Singapore Tops 90% Utilization as AI Drives Silicon Photonics Expansion
  • Synopsys and Amazon Announce Strategic, Multi-year IP Agreement for Custom Silicon; Collaboration Also Extends to Cloud and AI-Powered Engineering
  • IC Prototype Packaging: Options, Cost & Suppliers
  • Silicon Interposer vs Organic Interposer vs Glass Interposer: Which Is Best?
  • 2.5D vs 3D Packaging: What Is the Difference?

Most Popular Blog Posts

  • Semiconductor Manufacturing Cost Breakdown | Wafer, Packaging, Test & ASIC Cost Factors
  • TSMC and Sony Plan Image Sensor Joint Venture in Japan
  • Semiconductor Design and Verification Services | ASIC, SoC & IC Development Partners
  • ASIC Design Services for Startups | From Idea to Silicon
  • Custom ASIC Solutions | Find ASIC Design & Turnkey Chip Development Partners

Tools

  • ASIC Price Calculator
  • IC Packages Price Calculator
  • Die Per Wafer Calculator
  • Bonding Diagram Tool
  • CPU IP Core Search Engine
  • Find Consultants

We are using cookies to give you the best experience on our website. You can find out more about which cookies we are using or switch them off in settings. Accept

Reject

Close GDPR Cookie Settings

Privacy Overview

Strictly Necessary Cookies 3rd Party Cookies

Privacy Overview

This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.

Strictly Necessary Cookies

Strictly Necessary Cookie should be enabled at all times so that we can save your preferences for cookie settings. Enable or Disable Cookies

Enabled

Disabled

3rd Party Cookies This website uses Google Analytics to collect anonymous information such as the number of visitors to the site, and the most popular pages. Keeping this cookie enabled helps us to improve our website. Enable or Disable Cookies

Enabled

Disabled

Enable All Reject All

Bron 2026-10-05