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Next Gen, High-Speed, Memory and Cache Controller Design Engineer

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Published Date: October 09, 2026

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Qualcomm, San Diego, CA

Job Description

Qualcomm Technologies, Inc. is seeking a Senior ASIC Design Engineer to join its Engineering Group, specifically within the ASICS Engineering team. This role focuses on the design and development of high-speed memory controllers for next-generation products, contributing to Qualcomm's mission of driving innovation in communication and data processing.

Responsibilities

  • Define, model, design, optimize, verify, validate, implement, and document IP development for high-performance products.
  • Work on architecture, design (RTL coding), and deployment of high-speed memory systems into QCT products.
  • Develop architecture and design specifications and drive micro-architecture of logic design.
  • Implement and deliver RTL, collaborating with verification engineers to ensure high-quality designs.
  • Debug designs and provide support during integration into the chip.
  • Conduct synthesis, timing closure, physical design support, gate level simulations, and power analysis.
  • Contribute to the improvement of design methodology to enhance productivity and quality. Qualifications:
  • Bachelor's or Master's degree in Science, Engineering, or a related field.
  • 3 years of experience in ASIC design or related areas, or recent graduates are also encouraged to apply. Skills:
  • Experience with LPDDR memory and cache controller design.
  • Familiarity with NoC based architectures and front-end interfacing to CPU, DSP, and multimedia processors.
  • Exposure to HBM memory type designs.
  • Knowledge of on-chip tightly coupled SRAM & L3 cache controller architecture/design.
  • Experience with x86 or ARM CPU/bus architectures.
  • Understanding of memory transaction ordering and methods to enforce proper ordering according to ISA architecture specifications.

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