Startups

anysilicon.com

ASIC Failure Analysis Engineer [Hybrid]

<meta name="twitter:description" content="{"overview":"Cisco is seeking a Failure Analysis Engineer to join its Quality and Reliability group in San Jose, California. This hybrid role involves" /> You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 15 Views ASIC Failure Analysis Engineer [Hybrid]

Join Job Mailing List

Published Date: October 13, 2026

Apply

Cisco Systems, San Jose, CA

Job Description

Cisco is seeking a Failure Analysis Engineer to join its Quality and Reliability group in San Jose, California. This hybrid role involves approximately three days in the office and focuses on performing failure analysis of ASIC products. The ideal candidate will have a strong technical background in semiconductor failure analysis and a passion for problem-solving.

Responsibilities

  • Conduct root cause failure analysis of silicon product reliability test and field failures, proposing corrective actions.
  • Develop and implement standard processes for failure analysis using various FA equipment.
  • Coordinate logistics and instructions to direct the failure analysis process systematically.
  • Document and report failure analysis results to management.
  • Serve as a technical resource for failure analysis inquiries.
  • Develop and maintain relationships with FA service and equipment vendors.
  • Interface with product, test, and design engineering groups to identify and characterize faults on emerging technologies. Qualifications:
  • Bachelor's degree in Electrical/Electronics Engineering or related field required; Master's degree preferred.
  • 8 years of experience in semiconductor failure analysis.
  • Experience writing and executing FA plans and interpreting results from FA techniques such as cross-section, X-ray, CSAM, TDR, FIB, SEM, TEM, IR/EMMI/OBIRCH. Skills:
  • Proficient in specifying hardware and implementing setups for dynamic FA using SIL and LSM.
  • Experience with fault isolation techniques using ATE, Scan/ATPG, MBIST.
  • Knowledge of semiconductor technology and processes, including Fab, Assembly, and Advanced Packaging.
  • Understanding of transistor function, semiconductor device physics, and behavior under various operating conditions.

Recent Stories

CTO Talk: Denis Zelenin of Pacific MicroCHIP

Read More »

How to Choose the Right Arm CPU Core for ASIC

Read More »

MPW Run: Cost, Schedule & Booking Tool

Read More »

TSMC MPW: CyberShuttle, Cost, Schedule & Access

Read More »

High-end packaging: a market set to nearly quintuple by 2031

Read More »

IC Prototype Packaging: Options, Cost & Suppliers

Read More »

Silicon Interposer vs Organic Interposer vs Glass Interposer: Which Is Best?

Read More »

2.5D vs 3D Packaging: What Is the Difference?

Read More »

Get Price for ASIC Design Services

Get Price for IC Packaging

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

  • ASIC Design Services
  • Verification
  • Packaging & Wafer
  • Semiconductor IP

Work Email

Get Free Recommendations

Free • No obligation • Response within 24 hours Get Price Offers From ASIC Design Houses Wafer Foundries Chip Packaging

IC Testing

IP Core Vendors

FPGA Design

Featured Vendor

Experior

Welcome New Vendors

  • VConnecTech Systems
  • TOPPAN Technical Design Center
  • Digicomm Semiconductor
  • Tekmos
  • BitSim Now

Recent Posts

  • ElectraIC Launches the NEXUS N1 Series: A New Family of NVIDIA Jetson-Based AI Mini Supercomputers
  • Faraday Powers Intelligent Sensing with New 14nm MIPI C/D Combo PHY IP
  • Tessolve Secures $75 Million From Vector Line Capital to Fund Semiconductor Acquisitions
  • CTO Talk: Denis Zelenin of Pacific MicroCHIP
  • How to Choose the Right Arm CPU Core for ASIC
  • MPW Run: Cost, Schedule & Booking Tool

Most Popular Blog Posts

  • Semiconductor Manufacturing Cost Breakdown | Wafer, Packaging, Test & ASIC Cost Factors
  • TSMC and Sony Plan Image Sensor Joint Venture in Japan
  • Semiconductor Design and Verification Services | ASIC, SoC & IC Development Partners
  • ASIC Design Services for Startups | From Idea to Silicon
  • Custom ASIC Solutions | Find ASIC Design & Turnkey Chip Development Partners

Tools

  • ASIC Price Calculator
  • IC Packages Price Calculator
  • Die Per Wafer Calculator
  • Bonding Diagram Tool
  • CPU IP Core Search Engine
  • Find Consultants

We are using cookies to give you the best experience on our website. You can find out more about which cookies we are using or switch them off in settings. Accept

Reject

Close GDPR Cookie Settings

Privacy Overview

Strictly Necessary Cookies 3rd Party Cookies

Privacy Overview

This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.

Strictly Necessary Cookies

Strictly Necessary Cookie should be enabled at all times so that we can save your preferences for cookie settings. Enable or Disable Cookies

Enabled

Disabled

3rd Party Cookies This website uses Google Analytics to collect anonymous information such as the number of visitors to the site, and the most popular pages. Keeping this cookie enabled helps us to improve our website. Enable or Disable Cookies

Enabled

Disabled

Enable All Reject All

Bron 2026-10-14