ASIC Engineer, Foundry and IP - AnySilicon <meta name="twitter:description" content="{"overview":"Meta is seeking an experienced ASIC Engineer to join its Infrastructure Silicon team, which focuses on designing high-performance," /> You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 8 Views ASIC Engineer, Foundry and IP
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Published Date: October 05, 2026
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Meta, Austin, TX
Job Description
Meta is seeking an experienced ASIC Engineer to join its Infrastructure Silicon team, which focuses on designing high-performance, power-efficient ASICs for AI and immersive computing. The role involves collaboration with foundry partners and physical design teams to optimize silicon technologies and enhance product roadmaps.
Responsibilities
- Analyze and benchmark foundry process offerings with physical design teams to identify optimal technologies for product roadmaps.
- Drive early PPA evaluation of foundation IP drops by conducting preliminary PnR experiments to identify issues and opportunities for improvement.
- Architect, design, and characterize high-performance, low-power, and ultra-high-density standard cell libraries in collaboration with foundry partners and physical design teams.
- Run transistor-level simulations (SPICE), direct custom physical layouts, and manage automated library characterization flows.
- Evaluate, benchmark, and select third-party memory compilers (SRAM, Register Files, ROM) based on rigorous PPA and trade-off metrics.
- Participate in physical implementation and tape-out of silicon test chips aimed at validating new foundation IP and custom structures. Qualifications:
- 6 years of experience in a foundry team focusing on PPA analysis and engineering benchmarking.
- Deep understanding of CMOS device physics, digital circuit design, and advanced node layout constraints.
- Proven track record of participating in test chip tapeouts with hands-on experience in end-to-end design and sign-off.
- Expert-level command of design environments such as Cadence Virtuoso, HSPICE, and Spectre.
- Working knowledge of synthesis, PnR, STA, and PDV tools for block convergence on a test chip.
- High proficiency in scripting languages like Python, TCL, Perl, or SKILL for automating evaluation pipelines and data analysis. Skills:
- Foundry technology benchmarking
- PPA analysis
- Standard cell circuit design
- Memory compiler optimization
- Test chip design and testing
- Transistor-level simulation (SPICE)
- Physical design tools (Cadence, HSPICE, Spectre)
- Scripting (Python, TCL, Perl, SKILL)
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