ASIC Design Engineers — Design-for-Test [DFT] & Physical Design [Synthesis and Timing] – [Experienced, Lead, or Senior] - AnySilicon <meta name="twitter:description" content="{"overview":"Boeing Defense, Space and Security is seeking ASIC Design Engineers specializing in Design-for-Test (DFT) and Physical Design to join their team" /> You are using an outdated browser. Please upgrade your browser or activate Google Chrome Frame to improve your experience. 28 Views ASIC Design Engineers — Design-for-Test [DFT] & Physical Design [Synthesis and Timing] – [Experienced, Lead, or Senior]
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Published Date: October 04, 2026
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Boeing, Mountain View, CA
Job Description
Boeing Defense, Space and Security is seeking ASIC Design Engineers specializing in Design-for-Test (DFT) and Physical Design to join their team in Mountain View, CA. This role involves working on advanced digital subsystems for mission-critical aerospace applications, focusing on DFT architectures and physical design responsibilities.
Responsibilities
- Design and implement DFT architectures and test access mechanisms such as TAP/JTAG, IJTAG, and Boundary Scan.
- Develop and validate TAP/JTAG and IJTAG infrastructures; produce necessary artifacts and support ATPG pattern generation.
- Drive pattern generation, memory test validation, silicon debug, and post-silicon validation.
- Perform synthesis, equivalence checking, static timing analysis, and timing convergence at block and chip levels.
- Support clean netlist handoffs and timing closure by collaborating with RTL, verification, and backend partners.
- Contribute to methodology development, automation, and best practices for next-generation products.
- Troubleshoot complex timing and CDC issues and implement robust solutions.
- Coordinate with external partners on custom DFT interfaces and backend flows.
- Mentor engineers and lead technical efforts for senior/lead levels. Qualifications:
- Ability to obtain a US Security Clearance; US Citizenship required.
- Bachelor's degree in Engineering, Computer Science, or related field.
- 5 years of ASIC/FPGA design for test or physical design experience. Skills:
- Proficiency in scripting for automation and analysis (Tcl, Python, Perl).
- Strong analytical, problem-solving, and communication skills.
- Hands-on expertise with DFT tools and methodologies (e.g., TAP/JTAG, MBIST).
- Practical experience in synthesis and static timing analysis (STA).
- Familiarity with industry-standard EDA tools and DFT/physical design methodologies.
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